View K7N401801B-QC13_3291136.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

128kx36 & 256kx 18 pipelined n t ram tm - 1 - rev. 3.0 july 2006 k7n401801b k7n403601b 4mb ntram tm specification * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or simi- lar applications where product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procuremen t to which special terms or provisions may apply. 100 tqfp with pb only
128kx36 & 256kx 18 pipelined n t ram tm - 2 - rev. 3.0 july 2006 k7n401801b k7n403601b document title 128kx36 & 256kx18-bit pipelined n t ram tm revision history rev. no. 0.0 0.1 0.2 1.0 2.0 3.0 remark preliminary preliminary preliminary final final final history 1. initial document. 1. changed dc parameters icc ; from 350ma to 290ma at -16, from 330ma to 270ma at -15, from 300ma to 250ma at -13, i sb1 ; from 100ma to 80ma 1. add x32 org. and industrial temperature 1. final spec release 2. changed pin capacitance - cin ; from 5pf to 4pf - cout ; from 7pf to 6pf 1. remove x32 organization 2. remove -16 speed bin 1. change ordering information draft date may. 15. 2001 june. 12. 2001 aug. 11. 2001 nov. 15. 2001 nov. 17. 2003 jul. 03. 2006
128kx36 & 256kx 18 pipelined n t ram tm - 3 - rev. 3.0 july 2006 k7n401801b k7n403601b 4mb ntram (pipelined) ordering information note 1. c(i) [operating temperature] : c-commercial, i-industrial org. vdd (v) speed (ns) access time (ns) part number 256kx18 3.3 7.5 4.2 k7n401801b-qc(i) 1 13 128kx36 k7n403601b-qc(i) 1 13
128kx36 & 256kx 18 pipelined n t ram tm - 4 - rev. 3.0 july 2006 k7n401801b k7n403601b 128kx36 & 256kx18-bit pipelined n t ram tm the k7n403601b and k7n401801b are 4,718,592 bits syn- chronous static srams. the n t ram tm , or no turnaround random access memory utilizes all the bandwidth in any combination of operating cycles. address, data inputs, and al l control signals except output enable and linear burst order are synchronized to input clock. burst order control must be tied "high or low". asynchronous inputs include the sleep mode enable(zz). output enable controls the outputs at any given time. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off- chip write pulse generation and provides increased timing flexibility for incomming sig- nals. for read cycles, pipelined sram output data is temporarily stored by an edge trigered output register and then released to the output bufferes at the next rising edge of clock. the k7n403601b and k7n401801b are implemented with samsung s high performance cmos technology and is available in 100pin tqfp pa ckages. multiple power and ground pins minimize ground bounce. general description features logic block diagram ? v dd =3.3v+0.165v/-0.165v power supply. ? v ddq supply voltage 3.3v+0.165v/-0.165v for 3.3v i/o or 2.5v+0.4v/-0.125v for 2.5v i/o. ? byte writable function. ? enable clock and suspend operation. ? single read/write control pin. ? self-timed write cycle. ? three chip enable for simple depth expansion with no datacon- tention. ? interleaved burst or a linear burst mode. ? asynchronous output enable control. ? power down mode. ? ttl-level three-state outputs. ? 100-tqfp-1420a package. ? operating in commeical and industrial temperature range. fast access times parameter symbol -13 unit cycle time tcyc 7.5 ns clock access time tcd 4.2 ns output enable access time toe 4.2 ns we bw x clk cke cs 1 cs 2 cs 2 adv oe zz dqa 0 ~ dqd 7 or dqa 0 ~ dqb 8 address address register control logic a 0 ~a 1 36 or 18 dqpa ~ dqpd output buffer register data-in register data-in register k k k register burst address counter write address register write control logic control register k a [0:16]or a [0:17] lbo a 2 ~a 16 or a 2 ~a 17 a 0 ~a 1 (x=a,b,c,d or a,b) 128kx36 , 256kx18 memory array n t ram tm and no turnaround random access memory are trademarks of samsung,
128kx36 & 256kx 18 pipelined n t ram tm - 5 - rev. 3.0 july 2006 k7n401801b k7n403601b pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 pin tqfp (20mm x 14mm) dqpc dqc 0 dqc 1 v ddq v ssq dqc 2 dqc 3 dqc 4 dqc 5 v ssq v ddq dqc 6 dqc 7 v dd v dd v dd v ss dqd 0 dqd 1 v ddq v ssq dqd 2 dqd 3 dqd 4 dqd 5 v ssq v ddq dqd 6 dqd 7 dqpd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqpb dqb 7 dqb 6 v ddq v ssq dqb 5 dqb 4 dqb 3 dqb 2 v ssq v ddq dqb 1 dqb 0 v ss v dd v dd zz dqa 7 dqa 6 v ddq v ssq dqa 5 dqa 4 dqa 3 dqa 2 v ssq v ddq dqa 1 dqa 0 dqpa 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 a 6 a 7 cs 1 cs 2 bw d bw c bw b bw a cs 2 v dd v ss clk we cke oe adv n.c. n.c. a 8 81 a 9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 a 16 a 15 a 14 a 13 a 12 a 11 a 10 n.c. n.c. v dd v ss n.c. n.c. a 0 a 1 a 2 a 3 a 4 a 5 31 lbo pin name notes : 1. the pin 83 is reserved for address bit for the 8mb ntram. 2. a 0 and a 1 are the two least significant bits(lsb) of the address fiel d and set the internal burst counter if burst is desired. symbol pin name tqfp pin no. symbol pin name tqfp pin no. a 0 - a 16 adv we clk cke cs 1 cs 2 cs 2 bw x(x=a,b,c,d) oe zz lbo address inputs address advance/load read/write control input clock clock enable chip select chip select chip select byte write inputs output enable power sleep mode burst mode control 32,33,34,35,36,37 44,45,46,47,48,49 50,81,82,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 v dd v ss n.c. dqa 0 ~a 7 dqb 0 ~b 7 dqc 0 ~c 7 dqd 0 ~d 7 dqpa~p d v ddq v ssq power supply(+3.3v) ground no connect data inputs/outputs output power supply (2.5v or 3.3v) output ground 14,15,16,41,65,66,91 17,40,67,90 38,39,42,43,83,84 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 k7n403601b(128kx36)
128kx36 & 256kx 18 pipelined n t ram tm - 6 - rev. 3.0 july 2006 k7n401801b k7n403601b pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 pin tqfp (20mm x 14mm) n.c. n.c. n.c. v ddq v ssq n.c. n.c. dqb 8 dqb 7 v ssq v ddq dqb 6 dqb 5 v dd v dd v dd v ss dqb 4 dqb 3 v ddq v ssq dqb 2 dqb 1 dqb 0 n.c. v ssq v ddq n.c. n.c. n.c. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a 10 n.c. n.c. v ddq v ssq n.c. dqa 0 dqa 1 dqa 2 v ssq v ddq dqa 3 dqa 4 v ss v dd v dd zz dqa 5 dqa 6 v ddq v ssq dqa 7 dqa 8 n.c. n.c. v ssq v ddq n.c. n.c. n.c. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 a 6 a 7 cs 1 cs 2 bw b bw a cs 2 v dd v ss clk we cke oe adv n.c. n.c. a 8 81 a 9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 a 17 a 16 a 15 a 14 a 13 a 12 a 11 n.c. n.c. v dd v ss n.c. n.c. a 0 a 1 a 2 a 3 a 4 a 5 31 lbo k7n401801b(256kx18) n.c. n.c. pin name notes : 1. the pin 83 is reserved for address bit for the 8mb n t ram. 2. a 0 and a 1 are the two least significant bits(lsb) of the address field and set the internal burst counter if burst is desired. symbol pin name tqfp pin no. symbol pin name tqfp pin no. a 0 - a 17 adv we clk cke cs 1 cs 2 cs 2 bw x(x=a,b) oe zz lbo address inputs address advance/load read/write control input clock clock enable chip select chip select chip select byte write inputs output enable power sleep mode burst mode control 32,33,34,35,36,37, 44,45,46,47,48,49 50,80,81,82,99,100 85 88 89 87 98 97 92 93,94 86 64 31 v dd v ss n.c. dqa 0 ~a 8 dqb 0 ~b 8 v ddq v ssq power supply(+3.3v) ground no connect data inputs/outputs output power supply (2.5v or 3.3v) output ground 14,15,16,41,65,66,91 17,40,67,90 1,2,3,6,7,25,28,29,30, 38,39,42,43,51,52,53, 56,57,75,78,79,83,84 95,96 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
128kx36 & 256kx 18 pipelined n t ram tm - 7 - rev. 3.0 july 2006 k7n401801b k7n403601b function description the k7n403601b and k7n401801b are n t ram tm designed to sustain 100% bus bandwidth by eliminating tu rnaround cycle when there is transition from read to write, or vice versa. all inputs (with the exception of oe , lbo and zz) are synchronized to rising clock edges. all read, write and deselect cy cles are initiated by the adv input. subsequent burst addresses can be internally generated by t he burst advance pin (adv). adv should be driven to low once the de vice has been deselected in order to load a new address for nex t operation. clock enable(cke ) pin allows the operation of the chip to be suspended as long as necessary. when cke is high, all synchronous inputs are ignored and the internal device regi sters will hold their previous values. n t ram tm latches external address and initiates a cycle, when cke , adv are driven to low and all three chip enables(cs 1 , cs 2 , cs 2 ) are active . output enable(oe ) can be used to disable the output at any given time. read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in th e address register, cke is driven low, all three chip enables(cs 1 , cs 2 , cs 2 ) are active, the write enable input signals we are driven high, and adv driven low.the internal array is read between the first rising edge and the second ri sing edge of the clock and t he data is latched in the output register. at the second clock edge the data is driven out of the sram. also during read operation oe must be driven low for the device to drive out the requested data. write operation occurs when we is driven low at the rising edge of the clock. bw [d:a] can be used for byte write operation. the pipe- lined n t ram tm uses a late-late write cycle to utilize 100% of the bandwidth. at the first rising edge of the clock, we and address are registered, and the data associat ed with that address is required two cycle later. subsequent addresses are generated by adv high for the burst acce ss as shown below. the starti ng point of the burst seguence is provided by the external address. the burst address counter wraps around to its initial state upon completion. the burst sequence is determined by the state of the lbo pin. when this pin is low, linear burst sequence is selected. and when this pin is high, inte rleaved burst sequence is selected. during normal operation, zz must be driven low. when zz is driv en high, the sram will enter a power sleep mode after 2 cycles. at this time, internal state of the sram is pr eserved. when zz returns to low, the sram normally operates after 2 cycles of wake u p time. burst sequence table (interleaved burst, lbo =high) note : 1. lbo pin must be tied to high or low, and floating state must not be allowed . lbo pin high case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 bq table (linear burst, lbo =low) note : 1. lbo pin must be tied to high or low, and floating state must not be allowed . lbo pin low case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0
128kx36 & 256kx 18 pipelined n t ram tm - 8 - rev. 3.0 july 2006 k7n401801b k7n403601b state diagram for n t ram tm begin write burst write begin read write d s r e a burst read d s wr i t e d s read d s read ds wr i t e burst deselect b u r s t r e ad b u r st w r i t e read write burst burst notes : 1. an ignore clock edge cycle is not shown is the above diagram. this is because cke high only blocks the clock(clk) input and does not change the state of the device. 2. states change on the rising edge of the clock(clk) command action ds deselect read begin read write begin write burst begin read begin write continue deselect 3
128kx36 & 256kx 18 pipelined n t ram tm - 9 - rev. 3.0 july 2006 k7n401801b k7n403601b synchronous t ruth table notes : 1. x means "don t care". 2. the rising edge of clock is symbolized by ( ). 3. a continue deselect cycle can only be ent erd if a deselect cyc le is executed first. 4. write = l means write operation in write truth table. write = h means read operation in write truth table. 5. operation finally depends on status of asynchronous input pins(zz and oe ). cs 1 cs 2 cs 2 adv we bw x oe cke clk address accessed operation hxxlxxx l n/a not selected xlxlxxx l n/a not selected xxhlxxx l n/a not selected xxxhxxx l n/a not selected continue lhllhxl l external address begin burst read cycle xxxhxxl l next address continue burst read cycle lhllhxh l external address nop/dummy read xxxhxxh l next address dummy read lhllllx l external address begin burst write cycle xxxhxlx l next address continue burst write cycle lhlllhx l n/a nop/write abort xxxhxhx l next address write abort xxxxxxx h current address ignore clock write truth table (x36) notes : 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk( ). we bw a bw b bw c bw d operation hxxxx read l l h h h write byte a l h l h h write byte b l h h l h write byte c l h h h l write byte d lllll write all bytes l h h h h write abort/nop truth tables write truth table (x18) notes : 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk( ). we bw a bw b operation hxx read l l h write byte a l h l write byte b l l l write all bytes l h h write abort/nop
128kx36 & 256kx 18 pipelined n t ram tm - 10 - rev. 3.0 july 2006 k7n401801b k7n403601b asynchronous truth table operation zz oe i/o status sleep mode h x high-z read ll dq l h high-z write l x din, high-z deselected l x high-z notes 1. x means "don t care". 2. sleep mode means power sleep mode of which stand-by current does not depend on cycle time. 3. deselected means power sleep mode of which stand-by current depends on cycle time. capacitance* (t a =25 c, f=1mhz) *note : sampled not 100% tested. parameter symbol test condition typ max unit input capacitance c in v in =0v - 4 pf output capacitance c out v out =0v - 6 pf operating conditions at 3.3v i/o (0 c t a 70 c) * the above parameters are also guaranteed at industrial temperature range. parameter symbol min typ. max unit supply voltage v dd 3.135 3.3 3.465 v v ddq 3.135 3.3 3.465 v ground v ss 000v operating conditions at 2.5v i/o (0 c t a 70 c) * the above parameters are also guaranteed at industrial temperature range. parameter symbol min typ. max unit supply voltage v dd 3.135 3.3 3.465 v v ddq 2.375 2.5 2.9 v ground v ss 000v absolute maximum ratings* *note : stresses greater than those listed under "absolute maximum ratings " may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating c onditions for extended periods may affect reliability. parameter symbol rating unit voltage on v dd supply relative to v ss voltage on v ddq supply relative to v ss v dd -0.3 to 4.6 v v ddq v dd v voltage on input pin relative to v ss v in -0.3 to v dd +0.3 v voltage on i/o pin relative to v ss v io -0.3 to v ddq +0.3 v power dissipation p d 1.4 w storage temperature t stg -65 to 150 c operating temperature commercial t opr 0 to 70 c industrial t opr -40 to 85 c storage temperature range under bias t bias -10 to 85 c
128kx36 & 256kx 18 pipelined n t ram tm - 11 - rev. 3.0 july 2006 k7n401801b k7n403601b dc electrical characteristics (v dd =3.3v+0.165v/-0.165v, t a =0 c to +70 c) notes : 1.the above parameters are also guaranteed at industrial temperature range. 2. reference ac operating conditions and characteristics for input and timing. 3. data states are all zero. 4. in case of i/o pins, the max. v ih =v ddq +0.3v parameter symbol test conditions min max unit notes input leakage current(except zz) i il v dd =max ; v in =v ss to v dd -2 +2 a output leakage current i ol output disabled, -2 +2 a operating current i cc v dd =max , i out =0ma zz v il , cycle time t cyc min -13 - 250 ma 1,2 standby current i sb device deselected, i out =0ma, zz v il , f=max, all inputs 0.2v or v dd -0.2v -13 - 130 ma i sb1 device deselected, i out =0ma, zz 0.2v, f=0, all inputs=fixed (v dd -0.2v or 0.2v) -80ma i sb2 device deselected, i out =0ma, zz v dd -0.2v, f=max, all inputs v il or v ih -50ma output low voltage(3.3v i/o) v ol i ol =8.0ma - 0.4 v output high voltage(3.3v i/o) v oh i oh =-4.0ma 2.4 - v output low voltage(2.5v i/o) v ol i ol =1.0ma - 0.4 v output high voltage(2.5v i/o) v oh i oh =-1.0ma 2.0 - v input low voltage(3.3v i/o) v il -0.3* 0.8 v input high voltage(3.3v i/o) v ih 2.0 v dd +0.3** v 3 input low voltage(2.5v i/o) v il -0.3* 0.7 v input high voltage(2.5v i/o) v ih 1.7 v dd +0.3** v 3 v ss v ih v ss- 1.0v 20% t cyc (min) (v dd =3.3v+0.165v/-0.165v,v ddq =3.3v+0.165/-0.165v or v dd =3.3v+0.165v/-0.165v,v ddq =2.5v+0.4v/-0.125v, t a =0to70 c) test conditions * the above parameters are also guaranteed at industrial temperature range. parameter value input pulse level(for 3.3v i/o) 0 to 3.0v input pulse level(for 2.5v i/o) 0 to 2.5v input rise and fall time(measured at 20% to 80% for 3.3v i/o) 1.0v/ns input rise and fall time(measured at 20% to 80% for 2.5v i/o) 1.0v/ns input and output timing reference levels for 3.3v i/o 1.5v input and output timing reference levels for 2.5v i/o v ddq /2 output load see fig. 1
128kx36 & 256kx 18 pipelined n t ram tm - 12 - rev. 3.0 july 2006 k7n401801b k7n403601b ac timing characteristics (v dd =3.3v+0.165v/-0.165v, t a =0 c to +70 c) notes : 1. the above parameters are also guaranteed at industrial temperature range. 2. all address inputs must meet the specified setup and hold times for all rising clock(clk) edges when adv is sampl ed low and cs is sampled low. all other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 3. chip selects must be valid at each rising edge of clk(when adv is low) to remain enabled. 4. a write cycle is defined by we low having been registered into the device at adv low, a read cycle is defined by we high with adv low, both cases must meet setup and hold times. 5. to avoid bus contention, at a given voltage and temperature t lzc is more than t hzc. the specs as shown do no t imply bus contention because t lzc is a min. parameter that is worst case at totally different test conditions (0 c,3.465v) than t hzc , which is a max. parameter(worst case at 70 c,3.135v) it is not possible for two srams on the same board to be at such different voltage and temperature. parameter symbol -13 unit min max cycle time tcyc 7.5 - ns clock access time tcd - 4.2 ns output enable to data valid toe - 4.2 ns clock high to output low-z tlzc 1.5 - ns output hold from clock high toh 1.5 - ns output enable low to output low-z tlzoe 0 - ns output enable high to output high-z thzoe - 3.8 ns clock high to output high-z thzc - 3.8 ns clock high pulse width tch 3.0 - ns clock low pulse width tcl 3.0 - ns address setup to clock high tas 1.5 -ns cke setup to clock high tces 1.5 -ns data setup to clock high tds 1.5 -ns write setup to clock high (we , bw x) tws 1.5 -ns address advance setup to clock high tadvs 1.5 -ns chip select setup to clock high tcss 1.5 -ns address hold from clock high tah 0.5 - ns cke hold from clock high tceh 0.5 - ns data hold from clock high tdh 0.5 - ns write hold from clock high (we , bwe x) twh 0.5 - ns address advance hold from clock high tadvh 0.5 - ns chip select hold from clock high tcsh 0.5 - ns zz high to power down tpds 2 - cycle zz low to power up tpus 2 - cycle output load(b), (for t lzc , t lzoe , t hzoe & t hzc ) dout 353 ? / 1538 ? 5pf* +3.3v for 3.3v i/o 319 ? / 1667 ? fig. 1 * including scope and jig capacitance output load(a) dout zo=50 ? rl=50 ? vl=1.5v for 3.3v i/o v ddq /2 for 2.5v i/o /+2.5v for 2.5v i/o 30pf*
128kx36 & 256kx 18 pipelined n t ram tm - 13 - rev. 3.0 july 2006 k7n401801b k7n403601b sleep mode sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb2 . the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an asynchronous, active high input that causes the device to enter sleep mode. when the zz pin becomes a logic high, i sb2 is guaranteed after the time t zzi is met. any operation pending when entering sleep mode is not guaranteed to successful complete. therefore, sleep mode (read or write) must not be initiated until valid pend- ing operations are completed. similarly, when exiting sleep mode during t pus , only a deselect or read cycle should be given while the sram is transitioning out of sleep mode. sleep mode electrical characteristics description conditions symbol min max units current during sleep mode zz v ih i sb2 10 ma zz active to input ignored t pds 2 cycle zz inactive to input sampled t pus 2 cycle zz active to sleep current t zzi 2 cycle zz inactive to exit sleep current t rzzi 0 k t pds zz setup cycle t rzzi zz isupply all inputs (except zz) outputs (q) t zzi t pus zz recovery cycle deselect or read only high-z don t care i sb2 sleep mode waveform normal operation cycle deselect or read only
128kx36 & 256kx 18 pipelined n t ram tm - 14 - rev. 3.0 july 2006 k7n401801b k7n403601b clock cke address write cs adv oe data out timing waveform of read cycle notes : write = l means we = l, and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l, and cs 2 = l t ch t cl t ces t ceh t as t ah a1 a2 a3 t ws t wh t css t csh t oe t hzoe t lzoe t cd t oh t hzc q3-4 q3-3 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 q1-1 don t care undefined t cyc t advs t advh
128kx36 & 256kx 18 pipelined n t ram tm - 15 - rev. 3.0 july 2006 k7n401801b k7n403601b timing waveform of wrte cycle clock address write cs adv data in t ch t cl a2 a3 d2-1 d1-1 d2-2 d2-3 d2-4 d3-1 d3-2 d3-3 oe data out t ds t dh don t care undefined t cyc cke a1 d3-4 t ces t ceh notes : write = l means we = l, and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l, and cs 2 = l q0-4 t hzoe q0-3
128kx36 & 256kx 18 pipelined n t ram tm - 16 - rev. 3.0 july 2006 k7n401801b k7n403601b timing waveform of single read/write clock address write cs adv oe data in t ch t cl t ds t dh data out a2 a4 a5 d2 t oe t lzoe q1 don t care undefined t cyc cke t ces t ceh a1 a3 a7 a6 q3 q4 q7 q6 d5 notes : write = l means we = l, and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l, and cs 2 = l a9 a8
128kx36 & 256kx 18 pipelined n t ram tm - 17 - rev. 3.0 july 2006 k7n401801b k7n403601b timing waveform of cke operation clock address write cs adv oe data in t ch t cl data out a1 a2 a3 a4 a5 t ces t ceh don t care undefined t cyc cke t ds t dh d2 q4 q1 notes : write = l means we = l, and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l, and cs 2 = l t cd t lzc t hzc q3 a6
128kx36 & 256kx 18 pipelined n t ram tm - 18 - rev. 3.0 july 2006 k7n401801b k7n403601b timing waveform of cs operation clock address write cs adv oe data in t ch t cl data out a1 a2 a3 a4 a5 don t care undefined t cyc cke d5 q4 t ces t ceh q1 q2 t oe t lzoe d3 t cd t lzc notes : write = l means we = l, and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l, and cs 2 = l t hzc t dh t ds
128kx36 & 256kx 18 pipelined n t ram tm - 19 - rev. 3.0 july 2006 k7n401801b k7n403601b package dimensions 0.10 max 0~8 22.00 0.30 20.00 0.20 16.00 0.30 14.00 0.20 1.40 0.10 1.60 max 0.05 min (0.58) 0.50 0.10 #1 (0.83) 0.50 0.10 100-tqfp-1420a 0.65 0.30 0.10 0.10 max + 0.10 - 0.05 0.127 units ; millimeters/inches

▲Up To Search▲

Price & Availability of K7N401801B-QC13

	To Download K7N401801B-QC13 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .